Synchronization Support in 64-bit Out-Of-Order Superscalar Dual-Core RISC-V Processor

Yadav, S and Kumar, M and Sajin, S and Garag, SS and Varghese, K (2024) Synchronization Support in 64-bit Out-Of-Order Superscalar Dual-Core RISC-V Processor. In: 9th IEEE International Conference for Convergence in Technology, I2CT 2024, 5 April 2024 through 7 April 2024, Pune, India.

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Abstract

This paper discusses the implementation of atomic instructions in a dual-core 64-bit out-of-order superscalar processors based on the open-source RISC-V instruction set architecture. Leveraging the advantage of RISC-V's modularization characteristics, each core implements RV64IMAFDC extension and optional supervisor and user mode privilege levels. In this paper, we focus on the A-extension, the atomic instruction set extension. This extension introduces instructions that provide atomic memory operations, enabling synchronization across multiple RISC-V harts within the same memory space. Our goal is to present an efficient execution flow of atomic memory operation instructions and Load-Reserved/Store-Conditional instructions for a dual-core System-on-Chip. We subsequently verify the synchronization capabilities through the execution of a standalone game application on SoC implemented on a Xilinx Kintex UltraScale KU085 FPGA-based board. © 2024 IEEE.

Item Type:	Conference Paper
Publication:	2024 IEEE 9th International Conference for Convergence in Technology, I2CT 2024
Publisher:	Institute of Electrical and Electronics Engineers Inc.
Additional Information:	The copyright for this article belongs to Institute of Electrical and Electronics Engineers Inc.
Keywords:	Modular construction; Programmable logic controllers; Reduced instruction set computing; System-on-chip, AMO; Atomic memory; Dual-core; LR/SC; MESI; Multi-core processor; Out of order; RISC V; SCU; Superscalar, Synchronization
Department/Centre:	Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Date Deposited:	30 Jul 2024 10:36
Last Modified:	30 Jul 2024 10:36
URI:	http://eprints.iisc.ac.in/id/eprint/85629

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