Mazumder, S and Mandal, M and Bharath Kumar, M and Malingu, G and Roy, SK and Basu, K (2024) Measurement of Circuit Parasitics of a 200kW SiC based Stack. In: UNSPECIFIED, pp. 1120-1124.
PDF
con_pro_iee_app_pow_ele_con_exp_2024.pdf - Published Version Restricted to Registered users only Download (2MB) | Request a copy |
Abstract
Converters with high power density are becoming necessary in applications such as traction inverters and electric vehicles, where the inverter stage must process power in the range of a few hundred kilowatts. As the inverters are often hard-switched, SiC power modules can enable high power density due to superior switching, conduction loss, and thermal performance. However, due to the fast switching transients of SiC MOSFETs, circuit parasitics can significantly impact the switching dynamics resulting in prolonged oscillation, high device stress, and crosstalk and EMI-related issues. So, estimation of circuit parasitic is essential for optimal gate and power circuit layout design. The experimental measurement-based parasitic estimation technique is superior to the electromagnetic simulation-based approach when the internal geometry of the power module is unknown. This paper presents a systematic approach to estimating parasitic inductances of a 200 kW SiC-based stack. The accuracy of this proposed method is verified through experiment and electromagnetic simulation with the help of ANSYS Q3D Extractor. © 2024 IEEE.
Item Type: | Conference Paper |
---|---|
Publication: | Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC |
Publisher: | Institute of Electrical and Electronics Engineers Inc. |
Additional Information: | The copyright for this article belongs to Institute of Electrical and Electronics Engineers Inc. |
Keywords: | Electric inverters; Electric traction; Electromagnetic fields; Electromagnetic simulation; Inductance; Inductance measurement; Power MOSFET; Silicon; Timing circuits, Ansys Q3D extractor; Electromagnetic simulation; High-power-density; Inverter stage; Measurements of; Parasitic inductance measurement; Parasitic inductances; Parasitics; Power module; SiC stack, Silicon carbide |
Department/Centre: | Division of Electrical Sciences > Electrical Engineering |
Date Deposited: | 01 Jun 2024 06:20 |
Last Modified: | 01 Jun 2024 06:20 |
URI: | https://eprints.iisc.ac.in/id/eprint/85148 |
Actions (login required)
View Item |