Kumar, S and Banerjee, G (2024) An Improved Charge-Pump Design to Increase Tuning Range and Reduce Spurs in FMCW Radar Synthesizers. In: 37th International Conference on VLSI Design, VLSID 2024, 6 January 2024through 10 January 2024, Kolkata, West Bengal, pp. 96-100.
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Abstract
The fractional-N charge pump (CP) phase-locked loop (FnPLL) is frequently used to generate linear chirps in a Frequency Modulated Continuous Wave (FMCW) radar. At higher chirp rates, there is an increase in static phase error which leads to higher in-band phase noise of the PLL. To address this issue, multiple charge pumps are used in parallel to compensate for the static phase error, which results in a larger area requirement. Additionally, at higher control voltages, there is an increase in current mismatch which results in decreased tuning range and increased reference spur. To overcome these challenges, we propose a new charge pump design that reduces error current and area requirements. Our design is implemented in a 180-nm CMOS technology with a 1.8 V supply. The proposed charge pump achieves an increase in tuning range by more than 15, while limiting the error current � 1. © 2024 IEEE.
Item Type: | Conference Paper |
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Publication: | Proceedings of the IEEE International Conference on VLSI Design |
Publisher: | IEEE Computer Society |
Additional Information: | The copyright for this article belongs to IEEE Computer Society. |
Keywords: | Charge pump circuits; Chirp modulation; Continuous wave radar; Errors; Frequency modulation; Phase noise; Tuning; Variable frequency oscillators, Area requirement; Charge-pump; Chirp; Control voltages; Error current; Frequency-modulated-continuous-wave radars; Pump design; Reference spur; Static phase errors; Tuning ranges, Phase locked loops |
Department/Centre: | Division of Electrical Sciences > Electrical Communication Engineering |
Date Deposited: | 28 Aug 2024 05:28 |
Last Modified: | 28 Aug 2024 05:28 |
URI: | http://eprints.iisc.ac.in/id/eprint/84869 |
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