Behera, SP and Vaidya, M and Naugarhiya, A (2024) Low Loss Gate Engineered Superjunction Insulated Gate Bipolar Transistor for High Speed Application. In: 37th International Conference on VLSI Design, VLSID 2024, 6 January 2024 through 10 January 2024, Kolkata, West Bengal, pp. 1-5.
PDF
pro_iee_int_con_vls_des_des_2024.pdf - Published Version Restricted to Registered users only Download (223kB) | Request a copy |
Abstract
This article explains about electrical behavior of new Insulated Gate Bipolar Transistor (IGBT) by providing stepped oxide pattern at gate terminal with splitting N-poly structure in to three verticals. In order to form a stepped oxide pattern the bottom oxide thickness of the gate decreases from left to right. On the right side, the bottom oxide is thinner than the channel side. Furthermore, the oxide thickness along the channel wall has been kept thinner which increases Gate to emitter charges (QGE) in comparison to conventional SJ-IGBT. These additional charges also lead to increase output current which helps to decrease area-specific on-resistance (RonA) However, reduced gate to collector charges QGC) is offered by increased bottom oxide thickness along the channel, which improves switching performance of the device and make it good candidate for high speed application. The collective advancement in QGE and QGC enables fast switching and provide 67 reduced turn-off loss (Eoff). Additionally, in our study it is observed that modifiedworkfunction by replacing middle N-Poly with P-Poly reduces the peak electric field at the bottom side and enables 12 improvement in BV as compared to SJ-IGBT. © 2024 IEEE.
Item Type: | Conference Paper |
---|---|
Publication: | Proceedings of the IEEE International Conference on VLSI Design |
Publisher: | IEEE Computer Society |
Additional Information: | The copyright for this article belongs to IEEE Computer Society. |
Keywords: | Electric fields, Electrical behaviors; Eoff; Higher speed applications; Insulatedgate bipolar transistor (IGBTs); Low-loss; Oxide patterns; Oxide thickness; Stepped gate; Superjunctions; Von, Insulated gate bipolar transistors (IGBT) |
Department/Centre: | Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology) |
Date Deposited: | 28 Aug 2024 13:11 |
Last Modified: | 28 Aug 2024 13:11 |
URI: | http://eprints.iisc.ac.in/id/eprint/84868 |
Actions (login required)
View Item |