Mathew, S and Bhat, KN and Nithin, N and Rao, R (2023) Performance Enhancement of Dual Material Gate Junctionless FinFETs using Dielectric Spacer. In: IETE Journal of Research .
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Abstract
In this work, a detailed investigation is done on the effectiveness of various spacer materials having different spacer lengths (LSP), in improving the performance of Dual-Material Gate-Junctionless FinFET (DMG-JLFinFET). Various performance metrics, such as Drain Induced Barrier Lowering (DIBL), Sub-threshold Swing (SS), ON current (ION), OFF current (IOFF), ratio of ION to IOFF (ION/IOFF), and tunneling current (Itunn), are closely monitored at gate lengths (Lg) down to 10 nm. DIBL degradation of 3.46 mV/V and SS degradation of 4.97 mV/dec are observed when Lg scales down from 30 nm to 10 nm. Except for the case of Itunn, other performance metrics improve with an increase in dielectric constant and length of spacer materials. The optimum performance of DMG-JLFinFET with a channel length of 10 nm is obtained when LSP is 5 nm. Enhancement in analog performance metrics is observed when high κ materials are used as spacers. Transconductance Generation Factor (TGF) improves from 35.86 V�1 to 47.4 V�1 and intrinsic gain increases from 6.93 dB to 11.98 dB when high κ dielectric materials like TiO2 are incorporated as spacers in a DMG-JLFinFET. © 2023 IETE.
Item Type: | Journal Article |
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Publication: | IETE Journal of Research |
Publisher: | Taylor and Francis Ltd. |
Additional Information: | The copyright for this article belongs to Authors. |
Keywords: | Drain current; High-k dielectric; Ions; Titanium dioxide, 'current; Drain-induced barrier lowering; Dual-material gates; High κ spacer; High-κ; Junctionless FinFET; Performance metrices; Spacer materials; Sub-threshold swing; Subthreshold, FinFET |
Department/Centre: | Division of Interdisciplinary Sciences > Centre for Nano Science and Engineering |
Date Deposited: | 29 Apr 2024 07:31 |
Last Modified: | 29 Apr 2024 07:31 |
URI: | https://eprints.iisc.ac.in/id/eprint/84351 |
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