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Tyche: A Compact and Configurable Accelerator for Scalable Probabilistic Computing on FPGA

Jain, Y and Banerjee, U (2023) Tyche: A Compact and Configurable Accelerator for Scalable Probabilistic Computing on FPGA. In: 2023 IEEE High Performance Extreme Computing Conference, HPEC 2023, 25 September 2023- 29 September 2023, Virtual, Online.

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Official URL: https://doi.org/10.1109/HPEC58863.2023.10363588

Abstract

Probabilistic computing is an emerging computing paradigm which involves the systematic control and manipulation of unstable stochastic units called p-bits. Multiple p-bits are connected together to implement p-circuits which have been shown to be capable of solving interesting computationally hard problems. In this work, we present Tyche, a compact and configurable hardware accelerator for scalable probabilistic computing on FPGA. Our architecture allows p-circuits requiring different number of p-bits to be implemented using the same hardware. The use of a single p-bit computing core instead of an array of processing elements provides significant logic resource savings. A logarithmic adder tree is used for single-cycle weight logic computation while ensuring reasonable performance even for large number of p-bits. Various application-specific p-circuits are experimentally demonstrated using our proposed hardware accelerator implemented on Xilinx UltraScale+ FPGA, thus emphasizing the viability of practical scalable probabilistic computing on modern FPGAs. © 2023 IEEE.

Item Type: Conference Paper
Publication: 2023 IEEE High Performance Extreme Computing Conference, HPEC 2023
Publisher: Institute of Electrical and Electronics Engineers Inc.
Additional Information: The copyright for this article belongs to Institute of Electrical and Electronics Engineers Inc.
Keywords: Computation theory; Computer circuits; Stochastic systems; Timing circuits, Binary stochastic neuron; Boltzmann machines; Configurable accelerator; Integer factorization; Invertible logic; Ising machine; P-bit; P-circuit; Probabilistic computing; Stochastic neurons, Field programmable gate arrays (FPGA)
Department/Centre: Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Date Deposited: 01 Mar 2024 10:30
Last Modified: 01 Mar 2024 10:30
URI: https://eprints.iisc.ac.in/id/eprint/84052

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