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Neuromorphic Computing With Address-Event-Representation Using Time-to-Event Margin Propagation

Srivatsav, RM and Chakrabartty, S and Thakur, CS (2023) Neuromorphic Computing With Address-Event-Representation Using Time-to-Event Margin Propagation. In: IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 13 (4). pp. 1114-1124.

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Official URL: https://doi.org/10.1109/JETCAS.2023.3328916


Address-Event-Representation (AER) is a spike-routing protocol that allows the scaling of neuromorphic and spiking neural network (SNN) architectures. However, in conventional neuromorphic architectures, the AER protocol and in general, any virtual interconnect plays only a passive role in computation, i.e., only for routing spikes and events. In this paper, we show how causal temporal primitives like delay, triggering, and sorting inherent in the AER protocol itself can be exploited for scalable neuromorphic computing using our proposed technique called Time-to-Event Margin Propagation (TEMP). The proposed TEMP-based AER architecture is fully asynchronous and relies on interconnect delays for memory and computing as opposed to conventional and local multiply-and-accumulate (MAC) operations. We show that the time-based encoding in the TEMP neural network produces a spatio-temporal representation that can encode a large number of discriminatory patterns. As a proof-of-concept, we show that a trained TEMP-based convolutional neural network (CNN) can demonstrate an accuracy greater than 99 on the MNIST dataset and 91.2 on the Fashion MNIST Dataset. Overall, our work is a biologically inspired computing paradigm that brings forth a new dimension of research to the field of neuromorphic computing. © 2011 IEEE.

Item Type: Journal Article
Publication: IEEE Journal on Emerging and Selected Topics in Circuits and Systems
Publisher: Institute of Electrical and Electronics Engineers Inc.
Additional Information: The copyright for this article belongs to Author.
Keywords: Bioinformatics; Computer architecture; Encoding (symbols); Integrated circuit interconnects; Network architecture; Network coding; Neurons; Timing circuits, Address-event representation; Biological neural networks; Delay; Encodings; Integrated circuit interconnections; Neural-networks; Neuromorphic computing; Routing-protocol; Spiking neural network; Time to events, Neural networks
Department/Centre: Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Date Deposited: 01 Mar 2024 06:00
Last Modified: 01 Mar 2024 06:00
URI: https://eprints.iisc.ac.in/id/eprint/83855

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