Performance and Reliability Co-design of Ultra High Voltage LDMOS Devices

Variar, HB and Somayaji, J and Shrivastava, M (2022) Performance and Reliability Co-design of Ultra High Voltage LDMOS Devices. In: 2022 IEEE International Conference on Emerging Electronics, 11 - 14 Dec 2022, Bangalore.

PDF icee_2022.pdf - Published Version Restricted to Registered users only Download (5MB) | Request a copy

Abstract

This work presents the performance and re-liability (HCI, SOA and ESD) co-design insights of Ul-tra High Voltage (UHV) Laterally Diffused Metal Oxide Semiconductor (LDMOS) devices. Device design insights and performance optimization guidelines for four different types of UHV LDMOS devices (Conventional, RESURF, SOI and RESURF SOI) is systematically developed using 3D TCAD. For the first time, a step-by-step approach to design gate, drain and source field plates and its implications on the co-design of these four different UHV designs is investigated, which demonstrated significant improvement in the device breakdown without altering its ON-resistance. Finally, performance and HCI, ESD & SOA reliability benchmarking is done for the optimum designs of all four (i.e. Conventional, RESURF, SOI and RESURF SOI) UHV LDMOS architectures.

Item Type:	Conference Paper
Publication:	2022 IEEE International Conference on Emerging Electronics, ICEE 2022
Publisher:	Institute of Electrical and Electronics Engineers Inc.
Additional Information:	The copyright for this article belongs to Institute of Electrical and Electronics Engineers Inc.
Keywords:	ESD; Field plates; HCI; LDMOS; RESURF; SOA; Ultra high voltage
Department/Centre:	Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Date Deposited:	27 Jun 2023 06:18
Last Modified:	27 Jun 2023 06:18
URI:	https://eprints.iisc.ac.in/id/eprint/82167

Actions (login required)

View Item