Impact of Thin-oxide Gate on the On-Resistance of HV-PNP Under ESD Stress

Monishmurali, M and Kranthi, NK and Boselli, G and Shrivastava, M (2023) Impact of Thin-oxide Gate on the On-Resistance of HV-PNP Under ESD Stress. In: 61st IEEE International Reliability Physics Symposium, IRPS 2023, 26-30 March 2023, Monterey.

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Abstract

Physical insights into the impact of the thin-oxide polysilicon gate on the on-resistance of DeMOS-based HV-PNP are developed using detailed TCAD simulation. Turn-on and eventual failure mechanisms in HV-PNP are discussed. The impact of thin-oxide polysilicon placed over the N-Well and P-Well regions is investigated separately. The physics of regenerative bipolar degradation and its effect of dynamic on-resistance is understood as a function of thin-oxide placement. Furthermore, floating the thin-oxide gate mitigated regenerative bipolar degradation while having a faster lateral PNP trigger, resulting in the best case of on-resistance at all current levels. The insights developed in this work help to design compact high-voltage PNPs. © 2023 IEEE.

Item Type:	Conference Paper
Publication:	IEEE International Reliability Physics Symposium Proceedings
Publisher:	Institute of Electrical and Electronics Engineers Inc.
Additional Information:	The copyright for this article belongs to the Institute of Electrical and Electronics Engineers Inc.
Keywords:	ESD; Gate Field Effect; High Voltage PNP; On Resistance
Department/Centre:	Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Date Deposited:	07 Jul 2023 06:35
Last Modified:	07 Jul 2023 06:35
URI:	https://eprints.iisc.ac.in/id/eprint/82108

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