Investigation on the impact of External Layout-dependent Gate-Drain Capacitance on the Switching Dynamics of Si SJMOS

Mandal, M and Roy, SK and Basu, K (2022) Investigation on the impact of External Layout-dependent Gate-Drain Capacitance on the Switching Dynamics of Si SJMOS. In: 10th IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2022, 14 - 17 December 2022, Jaipur.

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Abstract

The external parasitic gate-drain capacitance is a constant capacitance that exists between the externally accessible gate and drain terminals of the power MOSFET, and it is contributed by the layout of the gate and drain nodes routed in the PCB. Due to its comparable magnitude with the internal gate-drain capacitance of the silicon superjunction MOSFETs, it can significantly affect the switching dynamics during the voltage-rise and voltage fall periods. This effect is even more pronounced for superjunction MOSFET with low current rating. In this work, a quantitative investigation of the impact of the parasitic gate-drain capacitance o the switching dynamics is presented and verified experimentally for a wide operating condition for a 650V and 12A silicon superjunction MOSFET.

Item Type:	Conference Paper
Publication:	10th IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2022
Publisher:	Institute of Electrical and Electronics Engineers Inc.
Additional Information:	The copyright for this article belongs to Institute of Electrical and Electronics Engineers Inc.
Keywords:	Capacitance; Dynamics; Power MOSFET; Silicon, CooLMOS; External parasitics; Gate-drain capacitance; Layout dependents; MOSFETs; Parasitic gate drain capacitance; Parasitics capacitance; Silicon superjunction MOSFET; Superjunctions; Switching dynamics, Polychlorinated biphenyls
Department/Centre:	Division of Electrical Sciences > Electrical Engineering
Date Deposited:	20 May 2023 04:51
Last Modified:	20 May 2023 04:51
URI:	https://eprints.iisc.ac.in/id/eprint/81607

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