Efficient Hardware Architectures for 2-D BCH Codes in the Frequency Domain for Two-Dimensional Data Storage Applications

Mondal, A and Garani, SS (2021) Efficient Hardware Architectures for 2-D BCH Codes in the Frequency Domain for Two-Dimensional Data Storage Applications. In: IEEE Transactions on Magnetics, 57 (5).

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Abstract

We propose fast and efficient hardware architectures for a 2-D Bose-Chaudhuri-Hocquenghem (BCH) code of size ntimes n , with a quasi-cyclic burst error correction capability of ttimes t , in the frequency domain for data storage applications. A fully parallel encoder with the ability to produce an output every clock cycle was designed. Using conjugate class properties of finite fields, the algorithmic complexity of the encoder was significantly reduced, leading to a reduction in the number of gates by about 94 of the brute-force implementation per 2-D inverse discrete finite field Fourier transform (IDFFFT) point for a 15times 15 , t=2 2-D BCH code. We also designed a pipelined, low-latency decoder for the above encoder. The algorithmic complexity of various pipeline stages of the decoder was reduced significantly using finite field properties, reducing the space complexity of the entire decoder. For a particular case of n=15 and t=2 , the architectures were implemented on a Kintex 7 KC-705 field-programmable gate array (FPGA) kit, giving high throughputs of 22.5 and 5.6 Gb/s at 100 MHz for the encoder and decoder, respectively. © 1965-2012 IEEE.

Item Type:	Journal Article
Publication:	IEEE Transactions on Magnetics
Publisher:	Institute of Electrical and Electronics Engineers Inc.
Additional Information:	The copyright for this article belongs to Institute of Electrical and Electronics Engineers Inc.
Keywords:	Computational complexity; Decoding; Digital storage; Error correction; Field programmable gate arrays (FPGA); Frequency domain analysis; Parallel processing systems; Pipelines; Signal encoding; Storage allocation (computer), Algorithmic complexity; Bose-chaudhuri-hocquenghem codes; Data storage applications; Frequency domains; Hardware architecture; Number of gates; Pipeline stages; Space complexity, Memory architecture
Department/Centre:	Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Date Deposited:	02 Mar 2023 09:59
Last Modified:	02 Mar 2023 09:59
URI:	https://eprints.iisc.ac.in/id/eprint/80838

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