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System-Level IEC ESD Failures in High-Voltage DeNMOS-SCR: Physical Insights and Design Guidelines

Kranthi, NK and Sarro, JD and Sankaralingam, R and Boselli, G and Shrivastava, M (2021) System-Level IEC ESD Failures in High-Voltage DeNMOS-SCR: Physical Insights and Design Guidelines. In: IEEE Transactions on Electron Devices, 68 (9). pp. 4242-4250.

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Official URL: https://doi.org/10.1109/TED.2021.3100810


A unique failure mechanism for International Electrotechnical Commission (IEC) stress through a common-mode (CM) choke is investigated. The presence of a CM choke in the stress path was found to change the current waveform shape that the electrostatic discharge (ESD) protection device experiences on-chip. Minor variations in the stress current waveform shape for specific IEC stress levels are found to cause an unexpected window failure in drain-extended nMOS silicon controlled rectifier (DeNMOS-SCR). The 3-D technology computer-aided (TCAD) simulations are used to understand the device behavior and failure under the peculiar two-pulse-shaped IEC current waveform attributed to the presence of a CM choke. DeNMOS-SCR failure sensitivity to different components of the unique pulse shape is studied in detail. A novel device architecture is proposed to increase the DeNMOS-SCR robustness against the peculiar two pulse stimuli. The proposed DeNMOS-SCR was found to eliminate the window failures against system-level IEC stress through a CM choke in communication pins in automotive ICs. The proposed concept is universal and can be extended to all high-voltage DeNMOS-SCRs. A detailed physical insight is provided for the operation of the engineered structure. © 1963-2012 IEEE.

Item Type: Journal Article
Publication: IEEE Transactions on Electron Devices
Publisher: Institute of Electrical and Electronics Engineers Inc.
Additional Information: The copyright for this article belongs to Institute of Electrical and Electronics Engineers Inc.
Keywords: Drain current; Electric rectifiers; Electrostatic devices; Electrostatic discharge, Computer aided; Electrostatic discharge protection device (ESD); Engineered structures; Failure mechanism; International Electrotechnical Commission; Novel device architectures; Waveform shape; Window failures, Failure (mechanical)
Department/Centre: Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Date Deposited: 21 Feb 2023 05:39
Last Modified: 21 Feb 2023 05:39
URI: https://eprints.iisc.ac.in/id/eprint/80505

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