Hybrid SHM-PWM for Common-Mode Voltage Reduction in Three-Phase Three-Level NPC Inverter

Sharifzadeh, M and Babaie, M and Chouinard, G and Al-Haddad, K and Portillo, R and Franquelo, LG and Gopakumar, K (2021) Hybrid SHM-PWM for Common-Mode Voltage Reduction in Three-Phase Three-Level NPC Inverter. In: IEEE Journal of Emerging and Selected Topics in Power Electronics, 9 (4). pp. 4826-4838.

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Abstract

This article proposes hybrid selective harmonic mitigation (SHM)-pulsewidth modulation (PWM) that is characterized by both features harmonic mitigation and elimination aimed to reduce the common-mode voltage (CMV) and to mitigate the selected nontriplen harmonics in a three-phase neutral-point-clamped (NPC) inverter. As CMV harmonic modeling only shows triplens, the specified triplens are eliminated using the selective harmonic elimination (SHE) operation to control CMV pulsewidths and consequently to mitigate CMV magnitude that appears as its root-mean-square (rms) reduction. The determined nontriplen harmonics are also mitigated using the SHM approach by the same cost function. The proposed hybrid SHM-PWM empowered by both harmonic elimination and mitigation is implemented on a three-phase NPC inverter to confirm its performance on reducing CMV through experimental and theoretical analyses. It is shown that hybrid SHM is superior over pure SHE or SHM in dealing with multiobjective system, including CMV reduction and no ntriplen harmonics mitigation. © 2013 IEEE.

Item Type:	Journal Article
Publication:	IEEE Journal of Emerging and Selected Topics in Power Electronics
Publisher:	Institute of Electrical and Electronics Engineers Inc.
Additional Information:	The copyright for this article belongs to Institute of Electrical and Electronics Engineers Inc
Keywords:	Cost functions; Electric inverters; Pulse width modulation, Common mode voltage; Harmonic elimination; Harmonic mitigation; Harmonic model; Multi objective; NPC inverters; Three level NPC inverter; Triplen harmonics, Harmonic analysis
Department/Centre:	Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Date Deposited:	24 Feb 2023 04:50
Last Modified:	24 Feb 2023 04:50
URI:	https://eprints.iisc.ac.in/id/eprint/80437

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