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A reduced component count five-level inverter topology for high reliability electric drives

Karthik, A and Loganathan, U (2020) A reduced component count five-level inverter topology for high reliability electric drives. In: IEEE Transactions on Power Electronics, 35 (1). pp. 725-732.

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Official URL: https://doi.org/10.1109/TPEL.2019.2913821


This paper presents a reduced component count five-level inverter topology based on the stacked cell approach to multilevel inverters. The proposed topology utilizes the fundamental properties of three-phase voltages to reduce the number of switches and flying capacitors to cut size, weight and costs while facilitating higher reliability, simpler wiring and lesser electromagnetic interference. The operational aspects of the topology such as circuit structure, modulation and capacitor balancing are explained, followed by an account of device stresses and reliability. A discussion of certain additional features such as fault tolerant operation, loss steering and common-mode elimination addresses the usefulness of the topology in practical situations. A comparison of the proposed topology with existing methods in terms of several parameters is then used to highlight its merits and features. Finally, experimental results obtained using an induction motor drive incorporating the topology are given, so as to validate the feasibility of the proposed approach. © 1986-2012 IEEE.

Item Type: Journal Article
Publication: IEEE Transactions on Power Electronics
Publisher: Institute of Electrical and Electronics Engineers Inc.
Additional Information: The copyright for this article belongs to Institute of Electrical and Electronics Engineers Inc.
Keywords: Balancing; Electric inverters; Electric motors; Electromagnetic pulse; Induction motors; Reliability; Topology, Fault tolerant operations; Five-level; Fundamental properties; Induction motor drive; Motor drive; Multilevel inverter; stacked; Three phase voltage, Electric drives
Department/Centre: Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Date Deposited: 08 Feb 2023 09:21
Last Modified: 08 Feb 2023 09:21
URI: https://eprints.iisc.ac.in/id/eprint/80076

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