Paul, M and Sampath Kumar, B and Gossner, H and Shrivastava, M (2020) Engineering Schemes for Bulk FinFET to Simultaneously Improve ESD/Latch-Up Behavior and Hot Carrier Reliability. In: IEEE Transactions on Electron Devices, 67 (7). pp. 2745-2751.
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Abstract
This article presents a simultaneous impact of selective contact silicidation, silicide, and junction engineering on bulk FinFET's electrostatic discharge (ESD) reliability, latch-up (LU) robustness, and hot carrier-induced (HCI) degradation. The investigations are performed using 3-D TCAD simulations. To maximize the robustness against HCI reliability and to improve the ESD/LU performance simultaneously, essential technology guidelines are derived based on physical insights developed. With the incorporation of proposed S/D contact silicide and junction engineering, the ESD robustness of FinFETs can be improved by a factor of 6× compared to conventional approaches. Besides, this is found to improve the overall HCI reliability of bulk FinFETs. Based on these design guidelines, hybrid contact/junction engineered scheme is proposed for the overall robustness of FinFET system-on-chips (SoC).
Item Type: | Journal Article |
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Publication: | IEEE Transactions on Electron Devices |
Publisher: | Institute of Electrical and Electronics Engineers Inc. |
Additional Information: | The copyright for this article belongs to Institute of Electrical and Electronics Engineers Inc. |
Keywords: | Electrostatic devices; Electrostatic discharge; FinFET; Reliability; Silicides; System-on-chip, Carrier induced; Conventional approach; ESD robustness; Hot carrier reliability; Selective contacts; Silicidation; System on chips (SoC); TCAD simulation, Hot carriers |
Department/Centre: | Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology) |
Date Deposited: | 06 Feb 2023 06:38 |
Last Modified: | 06 Feb 2023 06:38 |
URI: | https://eprints.iisc.ac.in/id/eprint/79855 |
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