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Bit topology selection algorithm in design of highly accurate CMOS digital attenuator for phased array system

Kumar, V and Sai Saravanan, G and Selvaraja, SK (2020) Bit topology selection algorithm in design of highly accurate CMOS digital attenuator for phased array system. In: Engineering Research Express, 2 (1).

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Official URL: https://doi.org/10.1088/2631-8695/ab6266


This paper presents a new attenuator bit topology selection algorithm for attenuator design to simultaneously achieve low amplitude and phase error with minimum insertion loss. The significance of this algorithm has been demonstrated by the design and implementation of 8-bit digital attenuator using 65 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology in 2.8 GHz to 4.0 GHz frequency band. To meet the 8-bit attenuation and phase error resolution, new phase compensated Pi-, T- and T-bridge attenuator bit topologies are proposed in place of conventional attenuator bits from 32 dB to 0.25 dB. Performance of this attenuator has been validated with the help of exhaustive post layout parasitic simulation results. The integrated attenuator has demonstrated the highest ever reported attenuation precision at lowest root mean square (RMS) phase error and RMS amplitude error, i.e., 8-bit performance with maximum insertion loss of 5.1 dB, maxmum RMS phase error of 0.78° and maximum RMS amplitude error of 0.1 dB, input referred 1 dB compression point (IP1 dB)> +14.8 dBm, input and output matching <-12 dB, in 2.8 GHz to 4.0 GHz with 1.55mm × 0.35mm chip area. This significant improvement in the attenuation precision, RMS amplitude and phase error of the integrated attenuator is the result of, systematic design approach, selection of each attenuator bit architecture using the proposed attenuator bit selection algorithm and incorporation of phase compensation techniques

Item Type: Journal Article
Publication: Engineering Research Express
Publisher: IOP Publishing Ltd
Additional Information: The copyright for this article belongs to the IOP Publishing Ltd
Keywords: CMOS integrated circuits; Error compensation; Insertion losses; Integrated circuit design; Metals; MOS devices; Oxide semiconductors; Topology, 1dB compression point; Amplitude and phase error; Complementary metal-oxide-semiconductor technologies; Design and implementations; Phased array systems; Root mean square (rms) phase errors; Selection algorithm; Systematic design approach, Electric attenuators
Department/Centre: Division of Interdisciplinary Sciences > Centre for Nano Science and Engineering
Date Deposited: 01 Feb 2023 12:09
Last Modified: 01 Feb 2023 12:09
URI: https://eprints.iisc.ac.in/id/eprint/79695

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