An Improved Codec Design Architecture for Irregular LDPC Codes Applicable to WiMAX

Shri, D and Mondal, A and Garani, SS (2022) An Improved Codec Design Architecture for Irregular LDPC Codes Applicable to WiMAX. In: ICECS 2022 - 29th IEEE International Conference on Electronics, Circuits and Systems, Proceedings, 24 - 26 October, Glasgow.

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Abstract

We propose the design architecture of the Low-density parity-check (LDPC) encoder and decoder based on the WiMAX standard (IEEE 802.16e). The design architectures were implemented on a Kintex-7 KC705 field-programmable gate array (FPGA) kit, for a rate 1/2 WiMAX LDPC code with a code length of 2304, containing twelve layers in the parity check matrix. A new null bypassing logic for irregular LDPC decoder is proposed. The tool reported a total power of 0.677 W for encoder with a throughput of 364 Gbps. The tool reported a total power of 1.009 W for the decoder with a throughput of 0.0785 Gbps (78.5 Mbps) for five iterations. Our architecture is also amenable for constructing non-binary LDPC codes where each bit of the non-binary code is binary coded and interleaved, useful for applications in optical transmission channels. Our architecture is also scalable for a wide range of quasi-cyclic code parameters.

Item Type:	Conference Paper
Publication:	ICECS 2022 - 29th IEEE International Conference on Electronics, Circuits and Systems, Proceedings
Publisher:	Institute of Electrical and Electronics Engineers Inc.
Additional Information:	The copyright for this article belongs to Institute of Electrical and Electronics Engineers Inc.
Keywords:	Decoding; Forward error correction; IEEE Standards; Integrated circuit design; Light transmission; Matrix algebra; Satellite communication systems; Signal encoding, Design architecture; Encoder-decoder; Field-programmable gate array implementations; Interleavings; Layered min-sum (MSA) algorithm; Low-density parity-check; Low-density parity-check codes; Low-density parity-check encoder/decoder; Min-sum; WiMAX, Field programmable gate arrays (FPGA)
Department/Centre:	Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Date Deposited:	01 Feb 2023 05:29
Last Modified:	01 Feb 2023 05:29
URI:	https://eprints.iisc.ac.in/id/eprint/79646

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