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An Optimized BCH Decoder Design Architecture for Adaptive M-ary Recording Channels

Gunasekaran, A and Jose, NC and Srinivasa Garani, S (2019) An Optimized BCH Decoder Design Architecture for Adaptive M-ary Recording Channels. In: 62nd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2019, 4 - 7 August 2019, United States, pp. 710-713.

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Official URL: https://doi.org/10.1109/MWSCAS.2019.8884872


Error correction codes (ECCs) are used in storage devices to overcome noise and to meet stringent reliability requirements. Multi-level recording channels such as flash, phase change memories etc. require adaptive ECC schemes attuned to the recording channel characteristics that degrade over time. Each bit within M-ary coded data is realized via binary encoding using Bose-Chaudhuri-Hocquenghem (BCH) codes and exchanging side information over M-parallel binary coded channels. Designing optimized BCH decoders becomes critical towards high performance decoding circuits. In this paper, we develop a novel pipelined decoding architecture for BCH codes for such applications. Our proposed architecture is 45.8 more area-efficient than the existing 2-stage pipelined architecture and realized by hardware sharing between the syndrome computation and Chien search stages of the pipeline. Implementation of the proposed design in Kintex-7 field programmable gate array (FPGA) achieves a throughput of 2.11 Gbps and synthesis with UMC's 45 nm technology achieves a throughput of 4.63 Gbps. © 2019 IEEE.

Item Type: Conference Paper
Publication: Midwest Symposium on Circuits and Systems
Publisher: Institute of Electrical and Electronics Engineers Inc.
Additional Information: The copyright for this article belongs to Institute of Electrical and Electronics Engineers Inc.
Keywords: Decoding; Error correction; Field programmable gate arrays (FPGA); Integrated circuit design; Logic Synthesis; Memory architecture; Phase change memory; Pipelines; Virtual storage, Bose-chaudhuri-hocquenghem codes; Error correction codes (ECCs); High performance decoding; Multi-level recording; Pipelined architecture; Proposed architectures; Recording channels; Reliability requirements, Channel coding
Department/Centre: Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Date Deposited: 07 Jan 2023 08:42
Last Modified: 07 Jan 2023 08:42
URI: https://eprints.iisc.ac.in/id/eprint/78873

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