A 5-level inverter topology using a single DC-link with reduced switch count for open-end induction motor drives

Ghosh Majumder, M and Yadav, AK and Gopakumar, K and Umanand, L and Krishna Raj, R and Franquelo, LG (2019) A 5-level inverter topology using a single DC-link with reduced switch count for open-end induction motor drives. In: 21st European Conference on Power Electronics and Applications, EPE 2019 ECCE Europe, 3 September - 5 September 2019, Genova.

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Abstract

A multilevel inverter scheme with reduced number of switches using a single DC-link for open-end induction motor drive (OEIM) is presented in this paper. The total inverter system with OEIM yields voltage Space Vector Locations (SVL) alike to a 5-Level inverter. This proposed system is obtained by supplying OEIM with 3-Level inverter from one side and capacitor fed 2-Level inverter from another side. The capacitor of the 2-Level inverter is balanced by Space Vector (SV) redundancy to its nominal voltage of V-dc/4 where V-dc is the DC-link voltage and the flying capacitors in 3-Level inverter is balanced by pole voltage redundancy to its nominal voltage of V-dc/2. The simulation and hardware results for steady and transient state operation are also presented in this paper. © 2019 EPE Association.

Item Type:	Conference Paper
Publication:	2019 21st European Conference on Power Electronics and Applications, EPE 2019 ECCE Europe
Publisher:	Institute of Electrical and Electronics Engineers Inc.
Additional Information:	The copyright for this article belongs to Institute of Electrical and Electronics Engineers Inc.
Keywords:	Electric drives; Electric motors; Induction motors; Power electronics; Pulse width modulation; Redundancy; Variable speed drives; Vector spaces; Voltage control, Adjustable speed drives; Induction motor drive; Inverter topologies; Multilevel converter; Multilevel inverter; Steady and transient state; Voltage source inverter; Voltage space vectors, Electric inverters
Department/Centre:	Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Date Deposited:	06 Jan 2023 07:49
Last Modified:	06 Jan 2023 07:49
URI:	https://eprints.iisc.ac.in/id/eprint/78824

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