ePrints@IIScePrints@IISc Home | About | Browse | Latest Additions | Advanced Search | Contact | Help

Designing Virtual Memory System of MCM GPUs

Pratheek, B and Jawalkar, N and Basu, A (2022) Designing Virtual Memory System of MCM GPUs. In: 55th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2022, 1 - 5 October 2022, Chicago, pp. 404-422.

[img] PDF
IEEE_MICRO_2022.pdf - Published Version
Restricted to Registered users only

Download (804kB)
Official URL: https://doi.org/10.1109/MICRO56248.2022.00036

Abstract

Multi-Chip Module (MCM) designs have emerged as a key technique to scale up a GPU's compute capabilities in the face of slowing transistor technology. However, the disaggregated nature of MCM GPUs with many chiplets connected via in-package interconnects leads to non-uniformity. We explore the implications of MCM's non-uniformity on the GPU's virtual memory. We quantitatively demonstrate that an MCM-aware virtual memory system should aim to 1 leverage aggregate TLB capacity across chiplets while limiting accesses to L2 TLB on remote chiplets, 2 reduce accesses to page table entries resident on a remote chiplet's memory during page walks. We propose MCM-aware GPU virtual memory (MGvm) that leverages static analysis techniques, previously used for thread and data placement, to map virtual addresses to chiplets and to place the page tables. At runtime, MGvm balances its objective of limiting the number of remote L2 TLB lookups with that of reducing the number of remote page table accesses to achieve good speedups (52, on average) across diverse application behaviors.

Item Type: Conference Paper
Publication: Proceedings of the Annual International Symposium on Microarchitecture, MICRO
Publisher: IEEE Computer Society
Additional Information: The copyright for this article belongs to IEEE Computer Society.
Keywords: Computer graphics; Memory architecture; Program processors; Static analysis; Table lookup; Virtual addresses, Address translation; Chiplet; Module design; Multi chip modules; Nonuniformity; Page table; Page table walker; Translation look aside buffers; Virtual memory; Virtual memory systems, Graphics processing unit
Department/Centre: Division of Electrical Sciences > Computer Science & Automation
Date Deposited: 04 Jan 2023 07:25
Last Modified: 04 Jan 2023 07:25
URI: https://eprints.iisc.ac.in/id/eprint/78728

Actions (login required)

View Item View Item