Performance and Reliability Co-design of LDMOS-SCR for Self-Protected High Voltage Applications On-Chip

Kranthi, NK and Kumar, BS and Salman, A and Boselli, G and Shrivastava, M (2019) Performance and Reliability Co-design of LDMOS-SCR for Self-Protected High Voltage Applications On-Chip. In: 31st International Symposium on Power Semiconductor Devices and ICs, ISPSD 2019, 19 May 2019-23 May 2019, Shanghai, pp. 407-410.

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Abstract

In this work we address turn-on vulnerability of conventional LDMOS-SCR devices under standard circuit operation window. This behavior is correlated with early ESD / SoA failure and power-to-fail scalability issue in HV LDMOS-SCR devices. The 3D TCAD is used to Develop physical insights into the performance and reliability limiters of LDMOS-SCR device. Different engineered designs are proposed to mitigate turn-on vulnerability and ESD power to fail scalability, while keeping channel performance and hot carrier degradation unaffected. © 2019 IEEE.

Item Type:	Conference Paper
Publication:	Proceedings of the International Symposium on Power Semiconductor Devices and ICs
Publisher:	Institute of Electrical and Electronics Engineers Inc.
Additional Information:	The copyright for this article belongs to Institute of Electrical and Electronics Engineers Inc.
Keywords:	Electrostatic devices; Electrostatic discharge; Integrated circuits; Scalability; Surge protection, Circuit operation; Co-designs; Engineered designs; High voltage applications; Hot carrier degradation; Laterally Double Diffused MOS (LDMOS); Performance and reliabilities; Scalability issue, MOS devices
Department/Centre:	Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Date Deposited:	27 Dec 2022 10:47
Last Modified:	27 Dec 2022 10:47
URI:	https://eprints.iisc.ac.in/id/eprint/78588

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