A systematic approach for acceleration of matrix-vector operations in cgra through algorithm-architecture co-design

Merchant, F and Vatwani, T and Chattopadhyay, A and Raha, S and Nandy, SK and Narayan, R and Leupers, R (2019) A systematic approach for acceleration of matrix-vector operations in cgra through algorithm-architecture co-design. In: 32nd International Conference on VLSI Design, VLSID 2019, 5 January 2019 - 9 January 2019, New Delhi, pp. 64-69.

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Abstract

Matrix-vector operations play pivotal role in engineering and scientific applications ranging from machine learning to computational finance. Matrix-vector operations have time complexity of O(n2) and they are challenging to accelerate since these operations are memory bound operations where ratio of the arithmetic operations to the data movement is O(1). In this paper, we present a systematic methodology of algorithm-architecture co-design to accelerate matrix-vector operations where we emphasize on the matrix-vector multiplication (gemv) and the vector transpose-matrix multiplication (vtm). In our methodology, we perform a detailed analysis of directed acyclic graphs of the routines and identify macro operations that can be realized on a reconfigurable data-path that is tightly coupled to the pipeline of a processing element. It is shown that the PE clearly outperforms state-of-the-art realizations of gemv and vtm attaining 135 performance improvement over multicore and 200 over general purpose graphics processing units. In the parallel realization on REDEFINE coarse-grained reconfigurable architecture, it is shown that the solution is scalable.

Item Type:	Conference Paper
Publication:	Proceedings - 32nd International Conference on VLSI Design, VLSID 2019 - Held concurrently with 18th International Conference on Embedded Systems, ES 2019
Publisher:	Institute of Electrical and Electronics Engineers Inc.
Additional Information:	The copyright for this article belongs to Institute of Electrical and Electronics Engineers Inc.
Keywords:	Closed loop control systems; Computer graphics; Directed graphs; Embedded systems; Graph theory; Graphics processing unit; Learning systems; Pipeline processing systems; Program processors; Reconfigurable architectures; Scalability; Vectors; VLSI circuits, Algorithm architectures; Coarse grained reconfigurable architecture; Dense linear algebra; Directed acyclic graph (DAG); Instruction level parallelism; Matrix vector multiplication; Matrix-vector; Scientific applications, Matrix algebra
Department/Centre:	Division of Interdisciplinary Sciences > Computational and Data Sciences Others
Date Deposited:	27 Dec 2022 05:50
Last Modified:	27 Dec 2022 05:50
URI:	https://eprints.iisc.ac.in/id/eprint/78580

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