Physical Insights into the Low Current ESD Failure of LDMOS-SCR and its Implication on Power Scalability

Karmel Kranthi, N and Sampath Kumar, B and Salman, A and Boselli, G and Shrivastava, M (2019) Physical Insights into the Low Current ESD Failure of LDMOS-SCR and its Implication on Power Scalability. In: 2019 IEEE International Reliability Physics Symposium, IRPS 2019, 31 March 2019 - 4 April 2019, Monterey.

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Abstract

A unique low current ESD failure during snapback region, which otherwise survive high current stress, is reported in LDMOS-SCR device. The failure is universal to LDMOS-SCR devices designed as self-protected MOS switch and found to be specific to a window of current between trigger and holding state, which can only be captured using high resistance load-line in TLP system. This resulted in severe power scalability issues in LDMOS-SCRs. In this work, while using systematic experiments and 3D TCAD simulations, we have developed detailed physical insights into the unique low current ESD failure phenomenon in LDMOS-SCR devices.

Item Type:	Conference Paper
Publication:	IEEE International Reliability Physics Symposium Proceedings
Publisher:	Institute of Electrical and Electronics Engineers Inc.
Additional Information:	The copyright for this article belongs to Institute of Electrical and Electronics Engineers Inc.
Keywords:	Electrostatic devices; Electrostatic discharge; Outages; Scalability, High current stress; High resistance; Laterally Double Diffused MOS (LDMOS); Low currents; MOS switches; Power scalability; Systematic experiment; TCAD simulation, MOS devices
Department/Centre:	Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Date Deposited:	27 Dec 2022 04:59
Last Modified:	27 Dec 2022 04:59
URI:	https://eprints.iisc.ac.in/id/eprint/78566

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