A Multilevel Inverter for Instantaneous Voltage Balancing of Single Sourced Stacked DC-Link Capacitors for an Induction Motor Load

Debnath, T and Resalayyan, R and Imthias, M and Gopakumar, K and Umanand, L and Jarzyna, W (2022) A Multilevel Inverter for Instantaneous Voltage Balancing of Single Sourced Stacked DC-Link Capacitors for an Induction Motor Load. In: IEEE Transactions on Power Electronics, 37 (9). pp. 10633-10641.

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Abstract

This article proposes a novel nine-level multilevel inverter topology with an instantaneous voltage balancing scheme of stacked dc-link capacitors for an induction motor (IM) drive application. Three neutral points (NPs, terminal joints of four series-connected capacitors) across a single dc-link are balanced instantaneously (within a sampling interval) by ensuring zero current at the NPs. The proper selection of pole voltage from the redundancies provides zero current at any NP during the pulsewidth modulation operation under a steady-state and transient operation. A five-level stacked inverter and three cascaded hybrid-bridge (CHB) inverter cells are used in each phase. Along with the balancing of dc-link capacitors, CHB capacitors' voltage balancing is also achieved using the pole voltage redundancies at all modulation indexes for all power factor and load. It is also possible to increase more number of levels using more low-voltage switches, and a generalized form of the topology is presented. The concept is validated using a laboratory-developed nine-level inverter with a three-phase IM load, operated under 'V/f' control. The detailed experimental results for the steady and transient condition, simulation studies for switching loss, and harmonic content in the phase voltage are also presented. © 1986-2012 IEEE.

Item Type:	Journal Article
Publication:	IEEE Transactions on Power Electronics
Publisher:	Institute of Electrical and Electronics Engineers Inc.
Additional Information:	The copyright for this article belongs to the Institute of Electrical and Electronics Engineers Inc.
Keywords:	Bridge circuits; Electric inverters; Induction motors; Poles; Power quality; Redundancy; Topology; Voltage control, Cascaded H-bridge; CCP; Common coupling; Common coupling point; Dc-link; Inductions motors; Inverte; Inverter; Multilevel inverter; Multilevels; Neutral points; Pulsewidth modulations (PWM); Single DC-link; Split dclink; Stacked, Pulse width modulation
Department/Centre:	Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Date Deposited:	06 Oct 2022 10:42
Last Modified:	06 Oct 2022 10:42
URI:	https://eprints.iisc.ac.in/id/eprint/77186

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