Measurement of Circuit Parasitics of SiC MOSFET in a Half-Bridge Configuration

Roy, SK and Basu, K (2022) Measurement of Circuit Parasitics of SiC MOSFET in a Half-Bridge Configuration. In: IEEE Transactions on Power Electronics, 37 (10). pp. 11911-11926.

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Abstract

Fast switching transient of SiC mosfet reduces switching loss. However, it excites device and circuit parasitics resulting in prolonged oscillation, high device stress, spurious turn on, EMI related issues, and higher switching loss. Behavioral or analytical models are used to estimate switching loss (dv/dt), (di/dt) rates, etc., and it requires the value of circuit parasitics as input. Measurement is the only way to accurately estimate some device package-dependent circuit parasitics when the internal package geometry is unknown. Hence, measurement of circuit parasitic is essential for optimal design. This article presents a set of simple experimental measurement techniques to determine circuit parasitic inductance and capacitances relevant for switching transient study of SiC mosfet in a half-bridge configuration. The accuracy of the proposed technique is verified through simulation and experimental results of the hard turn offand capacitor assisted soft turn-off dynamics of SiC mosfet over a range of operating conditions for two 1.2-kV discrete SiC mosfet of different current ratings and two different PCB layouts. Furthermore, the proposed technique is also validated with the existing frequency response analysis-based impedance measurement. © 1986-2012 IEEE.

Item Type:	Journal Article
Publication:	IEEE Transactions on Power Electronics
Publisher:	Institute of Electrical and Electronics Engineers Inc.
Additional Information:	The copyright for this article belongs to the Institute of Electrical and Electronics Engineers Inc.
Keywords:	Circuit simulation; Frequency response; Integrated circuits; Silicon carbide; Switching; Switching circuits; Timing circuits; Transient analysis, Dead time; Double pulse; Double pulse test; Frequency measurements; Hard switching; Integrated circuit modeling; Modeling; MOS-FET; MOSFETs; Parasitic measurement; Parasitics; Pulse test; SiC MOSFETs; Transmission-line measurements, MOSFET devices
Department/Centre:	Division of Electrical Sciences > Electrical Engineering
Date Deposited:	06 Oct 2022 10:16
Last Modified:	06 Oct 2022 10:16
URI:	https://eprints.iisc.ac.in/id/eprint/77181

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