A Low-complexity Hardware AWGN Channel Emulator on FPGA using Central Limit Theorem

Nair, AB and Mondal, A and Garani, SS (2019) A Low-complexity Hardware AWGN Channel Emulator on FPGA using Central Limit Theorem. In: 61st IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2018, 5 - 8 August 2018, Windsor, pp. 428-431.

PDF MWSCAS 2018_2019_428-431_2018.pdf - Published Version Restricted to Registered users only Download (175kB) | Request a copy

Abstract

We present a flexible, low-complexity additive white Gaussian noise (AWGN) channel emulator. The proposed generator employs multiple improved Tausworthe generators to generate uniform random numbers, which are then summed up and manipulated based on the central limit theorem to generate Gaussian random numbers. We simulated the hardware design with 12 and 48 Tausworthe random number generators (RNGs) with different seed sets. The proposed design provides one sample per clock useful towards high speed channel emulation.

Item Type:	Conference Paper
Publication:	Midwest Symposium on Circuits and Systems
Publisher:	Institute of Electrical and Electronics Engineers Inc.
Additional Information:	The copyright for this article belongs to the Institute of Electrical and Electronics Engineers Inc.
Keywords:	Field programmable gate arrays (FPGA); Gaussian distribution; Gaussian noise (electronic); Integrated circuit design; Noise generators; Number theory; White noise, Additive white Gaussian noise channel; Central Limit Theorem; channel emulation; Hardware design; Hardware emulation; High-speed channels; Random number generators; Random Numbers, Random number generation
Department/Centre:	Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Date Deposited:	16 Aug 2022 09:01
Last Modified:	16 Aug 2022 09:01
URI:	https://eprints.iisc.ac.in/id/eprint/75927

Actions (login required)

View Item