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On securing scan design from scan-based side-channel attacks

Ahlawat, S and Vaghani, D and Tudu, J and Singh, V (2018) On securing scan design from scan-based side-channel attacks. In: 26th IEEE Asian Test Symposium, ATS 2017, 27 - 30 November 2017, Taipei, pp. 54-59.

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Official URL: https://doi.org/10.1109/ATS.2017.23


Test and diagnosis requirements has made the use of scan design unavoidable for present day highly complex circuits. However, scan design can be exploited to retrieve the secret information stored on a crypto chip by mounting scan based side channel attack. The scan design poses a threat to the security of crypto chips as it gives the user the capability to control/observe the circuit state. In this paper, we propose a technique to secure the scan design that can effectively defend the crypto chips against scan based side-channel attacks. To use the scan architecture the user first needs to supply the test authorization key. Once the user is authorized, the conventional test sequence can be started. Furthermore, the proposed technique allows using the original test set without any test time and test data overhead. In addition to that, the proposed technique leaves the debug capability intact and has a marginal area overhead.

Item Type: Conference Paper
Publication: Proceedings of the Asian Test Symposium
Publisher: IEEE Computer Society
Additional Information: The copyright for this article belongs to the IEEE.
Keywords: Data privacy; Keys (for locks); Testing, Advanced Encryption Standard; Circuit state; Complex circuits; Lock-and-key; Scan architecture; Scan designs; Scan tests; Secret information, Side channel attack
Department/Centre: Division of Electrical Sciences > Computer Science & Automation
Date Deposited: 14 Aug 2022 05:25
Last Modified: 14 Aug 2022 05:25
URI: https://eprints.iisc.ac.in/id/eprint/75686

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