ePrints@IIScePrints@IISc Home | About | Browse | Latest Additions | Advanced Search | Contact | Help

Design Space Exploration of an Execution-Driven Functional Simulation Methodology

Mahapatra, IB and Agarwal, U and Azad, C and Nandy, SK (2018) Design Space Exploration of an Execution-Driven Functional Simulation Methodology. In: 31st International Conference on VLSI Design, VLSID 2018, 6 - 10 January 2018, Pune, pp. 295-300.

[img] PDF
IEEE_VLSID 2018_2018_295-300_2018.pdf - Published Version
Restricted to Registered users only

Download (883kB) | Request a copy
Official URL: https://doi.org/10.1109/VLSID.2018.79


Exploration of an efficient functional simulation methodology that has the capability to encounter conflicting conditions such as: maximizing hardware occupancy using efficient partitioning and mapping algorithms and minimizing inter hardware communication using optimized hardware dimensions, is very important. In this paper, we explore the design space of an execution-driven functional simulation methodology named EX-DRIVE. It performs functional simulation of a design under test (DUT) without the need for hardware synthesis and implementation of the DUT, offering significant improvement in functional simulation time. To realize this methodology we use a Network of Interconnected HyperCells (NIHC) as the meta platform. We explore the design space of EX-DRIVE for various dimensions of NIHC fabric and different partitioning and mapping algorithms. For this study we investigate six different hardware dimensions having a fixed hardware capacity and three partitioning and mapping algorithms: A Discrete Particle Swarm Optimization based algorithm (DPSO), a heuristic and a convex algorithm. We find that, for a fixed hardware capacity, the heuristic and convex algorithm proves to be more efficient for large and densely connected DUTs whereas the DPSO based algorithm proves to be more efficient for smaller and sparsely connected data flow graphs. The proposed algorithms are generic enough to be applied to any coarse grained re-configurable array assisted functional simulation platform.

Item Type: Conference Paper
Publication: Proceedings of the IEEE International Conference on VLSI Design
Publisher: IEEE Computer Society
Additional Information: The copyright for this article belongs to the IEEE Computer Society.
Keywords: Conformal mapping; Data flow analysis; Data flow graphs; Digital storage; Embedded systems; Hardware; Heuristic algorithms; Particle swarm optimization (PSO); VLSI circuits, Configurable hardware; Design space exploration; Design under tests; Discrete particle swarm optimization; Execution-driven simulation; Functional simulations; Mapping algorithms; VLSI, Design for testability
Department/Centre: Division of Interdisciplinary Sciences > Computational and Data Sciences
Division of Interdisciplinary Sciences > Centre for Nano Science and Engineering
Date Deposited: 08 Aug 2022 09:16
Last Modified: 08 Aug 2022 09:16
URI: https://eprints.iisc.ac.in/id/eprint/75608

Actions (login required)

View Item View Item