Two dimensional FFT architecture based on radix-43 algorithm with efficient output reordering

Kala, S and Nalesh, S and Jose, BR and Mathew, J and Ottavi, M (2018) Two dimensional FFT architecture based on radix-43 algorithm with efficient output reordering. In: 13th IEEE International Conference on Design and Technology of Integrated Systems In Nanoscale Era, DTIS 2018, 10 - 12 April 2018, Taormina, pp. 1-2.

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Abstract

In this paper we present a 64 × 64-point 2D FFT architecture using a parallel unrolled radix-43 (R43) FFT as the basic block. Our R43 architecture is a memory optimized parallel architecture which computes 64-point FFT, with least execution time. Here we use row-column decomposition of two R43 blocks to compute a 2D FFT. Proposed architecture has been implemented in UMC 40nm CMOS technology with clock frequency of 500 MHz, area of 0.841mm2 and power consumption of 358 mW. Computation time of 64 × 64 FFT is 8.19μs. ASIC results shows better performance of our FFT in terms of computation time when compared with state-of-art implementation.

Item Type:	Conference Paper
Publication:	Proceedings - 2018 13th IEEE International Conference on Design and Technology of Integrated Systems In Nanoscale Era, DTIS 2018
Publisher:	Institute of Electrical and Electronics Engineers Inc.
Additional Information:	The copyright for this article belongs to the Institute of Electrical and Electronics Engineers Inc.
Keywords:	Application specific integrated circuits; Integrated control; Nanotechnology; Parallel architectures, Architecture-based; Computation time; Efficient outputs; Execution time; Proposed architectures; Row column decomposition; Two-dimensional FFT; VLSI, Fast Fourier transforms
Department/Centre:	Division of Interdisciplinary Sciences > Computational and Data Sciences
Date Deposited:	11 Aug 2022 10:12
Last Modified:	11 Aug 2022 10:12
URI:	https://eprints.iisc.ac.in/id/eprint/75543

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