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Two-dimensional (2D) analytical investigation of an n-type junctionless gate-all-around tunnel field-effect transistor (JL GAA TFET)

Ajay, Ajay and Narang, R and Saxena, M and Gupta, M (2018) Two-dimensional (2D) analytical investigation of an n-type junctionless gate-all-around tunnel field-effect transistor (JL GAA TFET). In: Journal of Computational Electronics, 17 (2). pp. 713-723.

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Official URL: https://doi.org/10.1007/s10825-018-1151-7


Tunnel field-effect transistors have shown great potential given their good scalability and low leakage current. However, they are associated with some drawbacks, including ambipolar behavior and low ON-state current relative to the MOSFET. To overcome these problems, a novel junctionless gate-all-around TFET (JL GAA TFET) is proposed. The proposed device employs a two-dimensional model by solving Poisson’s equation in 2D. The results are verified with the assistance of Sentaurus Device simulation software. The electrical and electrostatic characteristics of the JL GAA TFET, including its surface potential, energy band, electric field, threshold voltage and drain current, are studied using models and simulations. The impact of various gate insulator materials is also studied using the model, and the transfer current of the JL GAA TFET is compared with that of a different type of FET device. The JL GAA TFET exhibits a high ION/ IOFF ratio (∼ 10 9) and a subthreshold slope of 28 mV/decade at room temperature for the high-kdielectric gate insulator material (TiO 2). With regard to the use of the device in switching applications, the JL GAA TFET appears to be a good candidate.

Item Type: Journal Article
Publication: Journal of Computational Electronics
Publisher: Springer New York LLC
Additional Information: The copyright for this article belongs to the Springer New York LLC.
Keywords: Analytical models; Computer software; Drain current; Electric fields; Insulating materials; Leakage currents; Poisson equation; Surface potential; Threshold voltage, Gate-all-around; Junctionless; Subthreshold slope; TCAD; Tunnel FET, Tunnel field effect transistors
Department/Centre: Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Date Deposited: 11 Aug 2022 09:39
Last Modified: 11 Aug 2022 09:39
URI: https://eprints.iisc.ac.in/id/eprint/75530

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