ePrints@IIScePrints@IISc Home | About | Browse | Latest Additions | Advanced Search | Contact | Help

Design and efficient implementation of censored cell averaging CFAR for non-homogeneous background

Narasimhan, RS and Vengadarajan, A and Ramakrishnan, KR (2018) Design and efficient implementation of censored cell averaging CFAR for non-homogeneous background. In: 2018 IEEE Aerospace Conference, AERO 2018, 3 - 10 March 2018, Big Sky, pp. 1-12.

[img] PDF
IEEE_AERO 2018_2018_1-12_2018.pdf - Published Version
Restricted to Registered users only

Download (527kB) | Request a copy
Official URL: https://doi.org/10.1109/AERO.2018.8396685


In this paper we propose the design of Censored Cell Averaging CFAR (CCA-CFAR) processor which does not require sorting of power levels in the reference cells. Cell Averaging (CA) CFAR is an optimum CFAR under exponential background interference and works well in homogeneous background. In real world radar detection problems, homogeneous background is a stricter requirement and CA CFAR exhibits performance degradation in the presence of interfering targets and clutter edges. Variants of CA CFAR such as Smaller Of (SO), Greater Of (GO), Variability Index (VI) CFAR, CATM CFAR are proposed in literature to handle the situation. The proposed CFAR processor is an extension of CA CFAR which selectively employs censoring of outliers in threshold computation. The proposed CFAR initially assumes that the background is homogeneous and employs CA CFAR to compute the threshold. Targets with sufficient SNR gets detected in this stage (stage-1). The range cells which cross the CA CFAR threshold are considered targets and these are considered outliers in background estimation. The background power estimate of range cells which include these outliers in the reference window is to be recomputed omitting these outliers. This is done in the second stage. In this stage, new targets might appear, which otherwise were masked in stage-1. We can run the outlier removal algorithm once again in the third stage considering the newly detected targets as outliers and remove their influence from the background estimate of affected range cells. The proposed Censored CA-CFAR processor (CCA-CFAR) effectively handles the detection loss caused due to the presence of interfering targets. We propose Switching Censored Cell-Averaging-Greater of CFAR processor (SCCAGO-CFAR) to handle the deficiencies of CCA-CFAR processor in the presence of clutter edges. In this CFAR processor we propose to dynamically switch CFAR between CA and GO CFAR in the first stage based on variability index and mean ratio, followed by censoring of outliers as in CCA-CFAR processor. Both the proposed CFAR processor do not require the ranking of reference cells based on return power and thus computationally efficient. The proposed technique is an extension of CA CFAR and belongs to class of mean level CFAR processors and can be implemented with a little higher processing requirement compared to CA CFAR. The censoring happens in stages, and outlier rejection step works on the small set of range cells thus adding small incremental load compared to CA CFAR. Simulations are carried out to evaluate the proposed CFAR techniques in handling abrupt clutter transitions and multiple interfering target environment. The approach is compared with other CFAR processors. The proposed approach works well in non-homogeneous background in the presence of multiple nearby targets. The of passes used to compute the threshold is also programmable and generally two to three passes are sufficient to detect targets in multiple-target environment.

Item Type: Conference Paper
Publication: IEEE Aerospace Conference Proceedings
Publisher: IEEE Computer Society
Additional Information: The copyright for this article belongs to the IEEE Computer Society.
Keywords: Cells; Clutter (information theory); Cytology; Radar clutter; Signal to noise ratio; Statistics; Tracking radar, Background estimation; Computationally efficient; Efficient implementation; Interfering targets; Multiple-target environments; Outlier rejection; Performance degradation; Variability index, Integrated circuit design
Department/Centre: Division of Electrical Sciences > Electrical Engineering
Date Deposited: 10 Aug 2022 08:59
Last Modified: 10 Aug 2022 08:59
URI: https://eprints.iisc.ac.in/id/eprint/75504

Actions (login required)

View Item View Item