FPGA based reconfigurable coprocessor for deep convolutional neural network training

Clere, SR and Sethumadhavan, S and Varghese, K (2018) FPGA based reconfigurable coprocessor for deep convolutional neural network training. In: 21st Euromicro Conference on Digital System Design, DSD 2018, 29 - 31 August 2018, Prague, pp. 381-388.

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Abstract

Deep Convolutional Neural Network (DCNN) is a class of machine learning algorithms that has wide application in pattern recognition, image recognition and video analysis. Convolutional layers in the network extract various features from a set of inputs and adapt parameters, before they do the classification. Training of DCNN is computationally intensive and has large memory requirement, but offers multiple degrees of parallelism, as similar structures are needed for computation at various intermediate stages. Training using a general purpose processing unit does not utilize parallelism of the network, and hence, is very time and energy inefficient. In this paper, we propose a coprocessor for accelerating the training of Convolutional Neural Network using a Xilinx Kintex Ultrascale XCKU085 based HTG-K800 FPGA board. DCNN is trained using back propagation algorithm. The coprocessor can be configured for a new network structure by changing the contents of Block Memory in the FPGA, without re-synthesizing and implementing using the design software. The reconfigurability through DDR can be supported with the architecture but is not implemented. The implementation achieves a maximum throughput of 280GOp/s.

Item Type:	Conference Paper
Publication:	Proceedings - 21st Euromicro Conference on Digital System Design, DSD 2018
Publisher:	Institute of Electrical and Electronics Engineers Inc.
Additional Information:	The copyright for this article belongs to Institute of Electrical and Electronics Engineers Inc.
Keywords:	Backpropagation; Backpropagation algorithms; Convolution; Coprocessor; Field programmable gate arrays (FPGA); Image recognition; Learning algorithms; Learning systems; Low power electronics; Network layers; Neural networks; Personnel training; Reconfigurable hardware; Systems analysis, Convolutional neural network; DCNN; Deep convolutional neural networks; Low Power; Maximum through-put; Memory requirements; Network structures; Re-configurability, Deep neural networks
Department/Centre:	Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Date Deposited:	04 Aug 2022 06:47
Last Modified:	04 Aug 2022 06:47
URI:	https://eprints.iisc.ac.in/id/eprint/75204

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