Method to Model Vccin Feedthrough Noise in Multi-Domain Fully Integrated Voltage Regulators

Govindan, S and Bharath, K and Gope, D and Venkataraman, S (2018) Method to Model Vccin Feedthrough Noise in Multi-Domain Fully Integrated Voltage Regulators. In: 27th IEEE Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2018, 14 - 17 October 2018, San Jose, pp. 151-153.

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Abstract

The on-chip power supply domains of high performance server microprocessors are generated using built-in switching voltage regulators (also know as Fully Integrated Voltage regulators-FIVRs). The advantages of integrated voltage generation are improved performance and reduced platform cost. However, the FIVRs share a common input power plane in the package and the coupling of noise between FIVRs is of significant concern. This noise is also known as the Vccin feedthrough noise. The modeling of the vccin feedthrough noise using circuit simulation tools such as SPICE is a laborious and time consuming task. This paper proposes a simple method to accurately predict the vccin feedthrough noise based on the state-space averaged small signal method. This method simplifies the modeling of vccin feedthrough noise and saves lot of time and effort.

Item Type:	Conference Paper
Publication:	EPEPS 2018 - IEEE 27th Conference on Electrical Performance of Electronic Packaging and Systems
Publisher:	Institute of Electrical and Electronics Engineers Inc.
Additional Information:	The copyright for this article belongs to Institute of Electrical and Electronics Engineers Inc.
Keywords:	Electric power systems; Electronics packaging; Packaging; Tools; Voltage regulators, And flows; Electronic package; EM interferences; Power distribution network; Simulation algorithms, SPICE
Department/Centre:	Division of Electrical Sciences > Electrical Communication Engineering
Date Deposited:	04 Aug 2022 06:06
Last Modified:	04 Aug 2022 06:06
URI:	https://eprints.iisc.ac.in/id/eprint/75154

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