Mishra, A and Shrivastava, M and Gupta, A (2022) The Root Cause Behind a Peculiar Dual-Mode ON-State Breakdown in High Voltage LDMOS. In: IEEE Transactions on Electron Devices, 69 (4). pp. 1906-1911.
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Abstract
This work investigates the often-observed current discontinuity much before avalanche breakdown (dual-mode ON-state breakdown) in the output characteristics of a laterally diffused metal-oxide-semiconductor (LDMOS) device. The physical origin of the dual-mode ON-state breakdown, often reasoned to be due to parasitic n-p-n, is shown to be independent of parasitic n-p-n. A laterally diffused tunnel FET (LDTFET) with a drift region profile same as LDMOS was experimented to rule out the effect of parasitic n-p-n. LDTFET device, which intrinsically cannot have parasitic n-p-n, also shows similar output characteristics with dual-mode ON-state breakdown. This proved that the parasitic bipolar turn-on is not the root cause behind the observed behavior. On the contrary, it was found to be dependent on the onset of space charge modulation (SCM) in the drift region, resulting in localized high electric field and quasi-saturation effects at low drain voltages. The effect of mobility degradation due to the high electric field in the drift region post-SCM is also presented, emphasizing that the observed behavior results from the high field mobility degradation of majority charge carriers. © 1963-2012 IEEE.
Item Type: | Journal Article |
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Publication: | IEEE Transactions on Electron Devices |
Publisher: | Institute of Electrical and Electronics Engineers Inc. |
Additional Information: | The copyright for this article belongs to the Institute of Electrical and Electronics Engineers Inc. |
Keywords: | Electric breakdown; Electric space charge; Impact ionization; Logic gates; Metals; Modulation; MOS devices; MOSFET devices; Oxide semiconductors, Charge modulation; Laterally diffused MOS; Laterally diffused tunnel FET; Lattice; Mobility degradation; On-state breakdown; Parasitic bipolar; Parasitics; Quasi-saturation; Safe operating area; Semiconductor process modeling; Space charge modulation ., Semiconductor doping |
Department/Centre: | Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology) |
Date Deposited: | 20 Jun 2022 11:50 |
Last Modified: | 20 Jun 2022 11:50 |
URI: | https://eprints.iisc.ac.in/id/eprint/73711 |
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