Skip-scan: A methodology for test time reduction

Kumar, Binod and Nehru, Boda and Pandey, Brajesh and Tudu, Jaynarayan (2017) Skip-scan: A methodology for test time reduction. In: ter Science and Automation, Indian Institute of Science, Bangalore, India, 24-27 May 2016, Guwahati, India, pp. 1-6.

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Abstract

Reducing test time is a major challenge in scan based DFT architectures for cost effective test. In this paper, we have proposed a test pattern reordering methodology for dynamic scan architecture. The reconfiguration of scan chain dynamically reduces its length by skipping scan cells with don't care bits. A graph theoretical approach is presented for test pattern reordering to maximise skip. We have calculated theoretical bounds on reduction in test time and segregated test patterns into groups with variable skip-depths. Our results indicate up to 84% reduction in test time. Comparison of this approach with the default ATPG tool pattern and scan chain reordering technique is also done.

Item Type:	Conference Paper
Publisher:	Institute of Electrical and Electronics Engineers Inc.
Additional Information:	The Copyright of this article belongs to the Institute of Electrical and Electronics Engineers Inc.
Keywords:	Dynamic scan; Pattern reordering; Scan DFT; Test Application time; Chains; Cost effectiveness; Graph theory; Integrated circuit testing; Memory architecture; Testing; VLSI circuits; Cost effective; Dynamic scan; Graph theoretical approach; Pattern reordering; Scan DFT; Test application time; Test time reduction; Theoretical bounds; Design for testability
Department/Centre:	Division of Electrical Sciences > Computer Science & Automation
Date Deposited:	13 Jun 2022 04:47
Last Modified:	13 Jun 2022 04:47
URI:	https://eprints.iisc.ac.in/id/eprint/73277

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