JSCAN: A joint-scan DFT architecture to minimize test time, pattern volume, and power

Tudu, Jaynarayan (2017) JSCAN: A joint-scan DFT architecture to minimize test time, pattern volume, and power. In: 20th International Symposium on VLSI Design and Test, VDAT 2016, 24-27 May 2016, Guwahati, India, pp. 1-6.

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Abstract

Traditionally, serial scan architecture have been predominantly used as a DFT technique for most of the designs. However, shrinking technology and increasing design complexity has brought a set of new test challenges. It initiates new research direction to explore innovative DFT architecture. This paper proposes a new DFT architecture, named as Joint-scan. The proposed architecture provides a solution for the test time, test data volume, and test power problems simultaneously. The primary idea here is to bring in the key advantages of serial scan and random access scan in a single architecture. The effectiveness of the proposed architecture has been demonstrated through experimental results by comparing with the state-of-the-art random access scan, and multiple sequential scan architecture. The results show promising reduction in test time, data volume, and test power.

Item Type:	Conference Paper
Publisher:	Institute of Electrical and Electronics Engineers Inc.
Additional Information:	The Copyright of this article belongs to the Institute of Electrical and Electronics Engineers Inc.
Keywords:	Architecture; Testing; VLSI circuits; Data volume; Design complexity; DFT architecture; Proposed architectures; Random access; Scan architecture; State of the art; Test-data volume; Design for testability
Department/Centre:	Division of Electrical Sciences > Computer Science & Automation
Date Deposited:	13 Jun 2022 04:46
Last Modified:	13 Jun 2022 04:46
URI:	https://eprints.iisc.ac.in/id/eprint/73276

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