Guided shifting of test pattern to minimize test time in serial scan

Tudu, Jaynarayan T and Ahlawat, Satyadev (2017) Guided shifting of test pattern to minimize test time in serial scan. In: 20th International Symposium on VLSI Design and Test, VDAT 2016, 24-27 May 2016, Guwahati, India, pp. 1-6.

PDF IEEE_VDAT_2016.pdf - Published Version Restricted to Registered users only Download (222kB) | Request a copy

Abstract

Scan test time has always been one of the priority issues for test researchers because it directly impact cost of the design. In this work we have addressed the issue through scan chain and test pattern reordering. The idea of limited scan shift is explored. We have proposed a graph theoretical framework for reordering of scan chain and test pattern. Graph theoretic problem is formulated for each, scan chain and test pattern, reordering. For each of the formulated problems corresponding approximation algorithms are proposed. The experimental results show that the proposed methodology reduces the scan shift time compared to the ordering provided by atpg tool.

Item Type:	Conference Paper
Publisher:	Institute of Electrical and Electronics Engineers Inc.
Additional Information:	The Copyright of this article belongs to the Institute of Electrical and Electronics Engineers Inc.
Keywords:	Approximation algorithms; Chains; Graph theory; VLSI circuits; ATPG tools; Formulated problems; Graph-theoretic problem; Impact costs; Scan tests; Shift time; Test Pattern; Theoretical framework; Integrated circuit testing
Department/Centre:	Division of Electrical Sciences > Computer Science & Automation
Date Deposited:	11 Jun 2022 09:13
Last Modified:	11 Jun 2022 09:13
URI:	https://eprints.iisc.ac.in/id/eprint/73275

Actions (login required)

View Item