Process technique for SEU reliability improvement of deep sub-micron SRAM cell

Saxena, PK and Bhat, N (2003) Process technique for SEU reliability improvement of deep sub-micron SRAM cell. In: Solid-State Electronics, 47 (4). pp. 661-664.

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Abstract

A technique is proposed to improve single event upset reliability of 0.09 μm SRAM cell by introducing an extra implant step similar to pocket halo, super steep retrograde channel and $V_t$ adjust implant steps in the existing process flow. It is shown that by changing the energy, dose and angle of implant, a heavily doped p+ region of high recombination rate can be introduced beneath the source/drain junctions. This results in decrease in effective charge collection volume, thereby increasing critical LET to flip the SRAM cell.

Item Type:	Journal Article
Publication:	Solid-State Electronics
Publisher:	Elsevier
Additional Information:	copyright of this article belongs to Elsevier.
Keywords:	Linear energy transfer;Super steep retrograde channel;Pocket halo;Dead layer
Department/Centre:	Division of Electrical Sciences > Electrical Communication Engineering
Date Deposited:	02 Jun 2006
Last Modified:	19 Sep 2010 04:28
URI:	http://eprints.iisc.ac.in/id/eprint/7325

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