Ferraz, O and Subramaniyan, S and Chinthalaa, R and Andrade, J and Cavallaro, JR and Nandy, SK and Silva, V and Zhang, X and Purnaprajna, M and Falcao, G (2022) A Survey on High-Throughput Non-Binary LDPC Decoders: ASIC, FPGA, and GPU Architectures. In: IEEE Communications Surveys and Tutorials, 24 (1). pp. 524-556.
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Abstract
Non-binary low-density parity-check (NB-LDPC) codes show higher error-correcting performance than binary low-density parity-check (LDPC) codes when the codeword length is moderate and/or the channel has bursts of errors. The need for high-speed decoders for future digital communications led to the investigation of optimized NB-LDPC decoding algorithms and efficient implementations that target high throughput and low energy consumption levels. We carried out a comprehensive survey of existing NB-LDPC decoding hardware that targets the optimization of these parameters. Even though existing NB-LDPC decoders are optimized with respect to computational complexity and memory requirements, they still lag behind their binary counterparts in terms of throughput, power and area optimization. This study contributes to an overall understanding of the state-of-the-art on application-specific integrated-circuit (ASIC), field-programmable gate array (FPGA) and graphics processing units (GPU) based systems, and highlights the current challenges that still have to be overcome on the path to more efficient NB-LDPC decoder architectures.
| Item Type: | Journal Article |
|---|---|
| Publication: | IEEE Communications Surveys and Tutorials |
| Publisher: | Institute of Electrical and Electronics Engineers Inc. |
| Additional Information: | The copyright for this article belongs to the authors |
| Keywords: | Application specific integrated circuits; Channel coding; Convolutional codes; Decoding; Digital communication systems; Energy utilization; Errors; Field programmable gate arrays (FPGA); Graphics processing unit; Program processors; Satellite communication systems; Signal encoding; Surveys; Throughput, Application-specific integrated circuits; Error correcting code; Error-correcting; High-throughput; Low density parity check decoding; Low-density parity-check; Non-binary; Non-binary low-density parity-check decoder; Nonbinary low-density paritycheck codes (LDPC); Resilient communications, Computer graphics |
| Department/Centre: | Division of Interdisciplinary Sciences > Computational and Data Sciences |
| Date Deposited: | 12 May 2022 11:15 |
| Last Modified: | 12 May 2022 11:15 |
| URI: | https://eprints.iisc.ac.in/id/eprint/71656 |
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