Ram, VSS and Panwar, A and Basu, A (2021) Trident: Harnessing architectural resources for all page sizes in x86 processors. In: 54th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2021, 18 October 2021, pp. 1106-1120.
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Abstract
Intel and AMD processors have long supported more than one large page sizes - 1GB and 2MB, to reduce address translation overheads for applications with large memory footprints. However, previous works on large pages have primarily focused on 2MB pages, partly due to a lack of evidence on the usefulness of 1GB pages to realworld applications. Consequently, micro-architectural resources devoted to 1GB pages have gone underutilized for a decade. We quantitatively demonstrate where 1GB pages can be valuable, especially when employed in conjunction with 2MB pages. Unfortunately, the lack of application-transparent dynamic allocation of 1GB pages is to blame for the under-utilization of 1GB pages on today's systems. Toward this, we design and implement Trident in Linux to fully harness micro-architectural resources devoted for all page sizes in the current x86 hardware by transparently allocating 1GB, 2MB, and 4KB pages as suitable at runtime. Trident speeds up eight memory-intensive applications by 18, on average, over Linux's use of 2MB pages. We then propose Tridentpv, an extension to Trident that virtualizes 1GB pages via copy-less promotion and compaction in the guest OS. Overall, this paper shows that adequate software enablement brings practical relevance to even GB-sized pages, and motivates micro-architects to continue enhancing hardware support for all large page sizes. © 2021 Association for Computing Machinery.
Item Type: | Conference Paper |
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Publication: | Proceedings of the Annual International Symposium on Microarchitecture, MICRO |
Publisher: | IEEE Computer Society |
Additional Information: | The copyright for this article belongs to Authors |
Keywords: | Linux, Address translation; Dynamic allocations; Large page; Memory footprint; Page sizes; Page table; Page table walk; Real-world; TLB; Virtual memory, Websites |
Department/Centre: | Division of Electrical Sciences > Computer Science & Automation |
Date Deposited: | 22 Nov 2021 10:32 |
Last Modified: | 22 Nov 2021 10:32 |
URI: | http://eprints.iisc.ac.in/id/eprint/70554 |
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