Polachan, K and Singh, C and Prabhakar, TV (2021) Decentralized Dynamic Gate Scheduling of IEEE 802.1Qbv Time Aware Shaper and a TSN Simulator for Tactile Cyber-Physical Systems. In: 17th IFIP/IEEE International Symposium on Integrated Network Management, IM 2021, 17-21 May 2021, Bordeaux17, pp. 45-53.
Full text not available from this repository.Abstract
Cybersickness and control-loop instabilities are two main concerns in Tactile Cyber-Physical Systems (TCPS). TCPS applications demand stringent bounds on end-to-end latencies to avoid their occurrences. Traditional best-effort networks cannot guarantee packet latencies in the presence of external traffic. On the other hand, emerging deterministic networks such as IEEE 802.1 Time Sensitive Networks (TSN) can isolate time-critical flows from external traffic using IEEE 802.1Qbv Time-Aware-Shaper (TAS) to guarantee bounded end-to-end packet latencies. In this work, we devise a decenteralized dynamic scheduling protocol to Configure non-overlapping gate slots in TAS enabled TSN switches to support TCPS flows. Our protocol supports plug-and-play operation of TCPS terminals with guaranteed minimal end-to-end packet latencies. Further, we also present PYTSN, an open-source discrete-event network simulator containing models of TAS enabled TSN switches and TCPS terminals. We use PYTSN to evaluate our proposed scheduling protocol. In particular, we show the isolation of TCPS flows from external traffic and plug and play operation of TCPS terminals. © 2021 IFIP.
| Item Type: | Conference Paper |
|---|---|
| Publication: | Proceedings of the IM 2021 - 2021 IFIP/IEEE International Symposium on Integrated Network Management |
| Publisher: | Institute of Electrical and Electronics Engineers Inc. |
| Additional Information: | The copyright for this article belongs to Institute of Electrical and Electronics Engineers Inc. |
| Keywords: | Control systems; Cyber Physical System; Discrete event simulation; Dynamics; Embedded systems; Network management; Scheduling, Best effort networks; Discrete-event network simulators; Dynamic scheduling; End to end latencies; Gate scheduling; Packet latencies; Plug and play; Scheduling protocol, IEEE Standards |
| Department/Centre: | Division of Electrical Sciences > Electrical Engineering |
| Date Deposited: | 03 Dec 2021 06:48 |
| Last Modified: | 03 Dec 2021 06:48 |
| URI: | http://eprints.iisc.ac.in/id/eprint/70096 |
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