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ATPG With Efficient Testability Measures and Partial Fault Simulation

Jain, Kamal Kumar and Jacob, James and Srinivas, MK (1991) ATPG With Efficient Testability Measures and Partial Fault Simulation. In: 1991 Fourth CSI/IEEE International Symposium on VLSI Design, 4-8 January, New Delhi,India, pp. 35-40.


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In this paper we propose an improved version of the test generation algorithm PODBM (Path Oriented Decision Making) incorporating a different technique for back tracing and forward implication. We also propose a partial fault simulator which is integrated into the improved PODEM algorithm. The performance of this test generation package (when partial fault simulator is employed) is compared to that of a concurrent fault simulator using deterministically generated test patterns. It is shown that the runtime performance of our algorithm compares favourably with that of the concurrent fault simulator and is less memory intensive. We also present effective heuristics to determine some of the redundant faults and to derive the test vectors for some PI faults, by the use of implication relations. Experimental results on all the 10 ISCAS benchmark circuits [7] demonstrate that our algorithm is faster and more efficient than the PODEM algorithm for these circuits.

Item Type: Conference Paper
Publisher: IEEE
Additional Information: Copyright 1990 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Department/Centre: Division of Interdisciplinary Sciences > Supercomputer Education & Research Centre
Division of Electrical Sciences > Electrical Communication Engineering
Division of Electrical Sciences > Computer Science & Automation
Date Deposited: 29 May 2006
Last Modified: 19 Sep 2010 04:27
URI: http://eprints.iisc.ac.in/id/eprint/7001

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