Molin, J and Thakur, C and Niebur, E and Etienne-Cummings, R (2021) A Neuromorphic Proto-Object Based Dynamic Visual Saliency Model with a Hybrid FPGA Implementation. In: IEEE Transactions on Biomedical Circuits and Systems, 15 (3). pp. 580-594.
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Abstract
Computing and attending to salient regions of a visual scene is an innate and necessary preprocessing step for both biological and engineered systems performing high-level visual tasks including object detection, tracking, and classification. Computational bandwidth and speed are improved by preferentially devoting computational resources to salient regions of the visual field. The human brain computes saliency effortlessly, but modeling this task in engineered systems is challenging. We first present a neuromorphic dynamic saliency model, which is bottom-up, feed-forward, and based on the notion of proto-objects with neurophysiological spatio-Temporal features requiring no training. Our neuromorphic model outperforms state-of-The-Art dynamic visual saliency models in predicting human eye fixations (i.e., ground truth saliency). Secondly, we present a hybrid FPGA implementation of the model for real-Time applications, capable of processing 112× 84 resolution frames at 18.71 Hz running at a 100 MHz clock rate-a 23.77× speedup from the software implementation. Additionally, our fixed-point model of the FPGA implementation yields comparable results to the software implementation. © 2007-2012 IEEE.
| Item Type: | Journal Article |
|---|---|
| Publication: | IEEE Transactions on Biomedical Circuits and Systems |
| Publisher: | Institute of Electrical and Electronics Engineers Inc. |
| Additional Information: | The copyright for this article belongs to Author |
| Keywords: | Application programs; Object detection; Object recognition; Object tracking; Vision; Visualization, Computational bandwidth; Computational resources; FPGA implementations; Neuromorphic modeling; Real-time application; Software implementation; Spatio temporal features; Visual saliency model, Field programmable gate arrays (FPGA) |
| Department/Centre: | Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology) |
| Date Deposited: | 20 Nov 2021 11:36 |
| Last Modified: | 20 Nov 2021 11:36 |
| URI: | http://eprints.iisc.ac.in/id/eprint/69902 |
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