An Algorithm for Discrete Event Logic Simulation on Distributed Systems

Sundaram, S and Mohan, TS and Patnaik, LM (1991) An Algorithm for Discrete Event Logic Simulation on Distributed Systems. In: 1991 IEEE Region 10 International Conference on EC3-Energy, Computer, Communication and Control Systems, TENCON '91, 28-30 August, New Delhi,India, Vol.3, 185-189.

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Abstract

Increase in the complexity of VLSI digital circuit design demands faster logic simulation techniques than those currently available. One of the ways of spreading up existing logic simulation algorithms is by exploiting the inherent parallelism of the sequential version. In this paper, we explore the possibility of mapping an event driven logic simulation algorithm onto a cluster of processors interconnected by an ethernet. The set of events at any simulation time step is partitioned by the Master Task (running on the host processor) among the Worker Tasks(running on the other processors). The partitioning scheme ensures a balanced load. Each Worker Task determines the fanout elements , evaluates them independently and comes up with the new event list which is passed onto the Master Task. After receiving the event lists from all the Workers, the Master Task increments the simulation time step, computes the new event list partition for the next simulation cycle. We have implemented this distributed logic simulation algorithm on a set of 8 VAX stations using CT-package for distributed programming. The paper concludes with a note on the speedup figures obtained on the ISCAS benchmark circuits.

Item Type:	Conference Paper
Publisher:	IEEE
Additional Information:	Copyright 1990 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Department/Centre:	Division of Interdisciplinary Sciences > Supercomputer Education & Research Centre Division of Electrical Sciences > Computer Science & Automation
Date Deposited:	24 May 2006
Last Modified:	19 Sep 2010 04:27
URI:	http://eprints.iisc.ac.in/id/eprint/6855

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