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Design of a 32-bit, dual pipeline superscalar RISC-V processor on FPGA

Gokulan, T and Muraleedharan, A and Varghese, K (2020) Design of a 32-bit, dual pipeline superscalar RISC-V processor on FPGA. In: Proceedings - Euromicro Conference on Digital System Design, DSD 2020, 26-28 August 2020, Kranj; Slovenia, pp. 340-343.

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Official URL: https://dx.doi.org/10.1109/DSD51259.2020.00062


A 40 MHz, 32-bit, 5-stage dual-pipeline superscalar processor based on RISC-V Instruction Set Architecture is presented. It supports integer, multiply-divide and atomic readmodify-write operations. The proposed system implements inorder issuing of instructions. The design incorporates a dynamic branch prediction unit, memory subsystem with virtual memory, separate instruction cache and data cache, integer and floating point execution units, interrupt controller, error control module, and a UART peripheral. The interrupt controller supports four levels of preemptive priority, which is programmable for individual interrupts. Error control module provides single error correction and double error detection for the main memory. Wishbone B.3 bus standard is adopted for on-chip communication. The processor is implemented on Virtex-7 XC7VX485TFFG1761-2 FPGA based board. CoreMark and Dhrystone benchmark values for the design are 3.84/MHz and 1.0603 DMIPS/MHz respectively. © 2020 IEEE.

Item Type: Conference Paper
Publication: Proceedings - Euromicro Conference on Digital System Design, DSD 2020
Publisher: Institute of Electrical and Electronics Engineers Inc.
Additional Information: cited By 0; Conference of 23rd Euromicro Conference on Digital System Design, DSD 2020 ; Conference Date: 26 August 2020 Through 28 August 2020; Conference Code:163851
Keywords: Cache memory; Controllers; Digital arithmetic; Error correction; Field programmable gate arrays (FPGA); Memory architecture; Pipeline processing systems; Pipelines; Systems analysis, Instruction caches; Instruction set architecture; Interrupt controllers; Memory subsystems; On chip communication; Preemptive priority; Single error corrections; Superscalar Processor, Integrated circuit design
Department/Centre: Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Date Deposited: 23 Dec 2020 11:18
Last Modified: 23 Dec 2020 11:18
URI: http://eprints.iisc.ac.in/id/eprint/67208

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