Fully Printed Vertical Transport Edge FETs for High Power Oxide Electronics

Devabharathi, N and Mondal, SK and Pradhan, JR and Dasgupta, S (2020) Fully Printed Vertical Transport Edge FETs for High Power Oxide Electronics. In: 4th Electron Devices Technology and Manufacturing Conference, EDTM 2020 - Proceedings, 6-21 April 2020, Penang, Malaysia, Malaysia.

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Abstract

One of the major challenges for printed electronics (PE) that lowers the performance of the solution-processed/printed field-effect transistors (FETs) and logics are the limited printing resolution, which at best lies in the micrometer range. In this regard, various concepts have been proposed and exercised to overcome the problem; however, the actual demonstration of high On-currents/channel conductance has been rare. In this context, we have conceived an innovative device architecture that allows easy printing of edge-FETs, with vertical transport of drain currents along a metal-semiconductor junction. In this manner, we have been able to bypass the low printing resolution problem. In the present work, we report fully printed FETs with a top gate architecture, where an extraordinary ON-current of 6 mA (about 100 μA μm) can be recorded. Such high device currents alongside excellent On/Off ratio (> 107) and very low variability enable the present technology to be extremely suitable for printed high power electronic applications. © 2020 IEEE.

Item Type:	Conference Paper
Publication:	4th Electron Devices Technology and Manufacturing Conference, EDTM 2020 - Proceedings
Publisher:	Institute of Electrical and Electronics Engineers Inc.
Additional Information:	cited By 0; Conference of 4th Electron Devices Technology and Manufacturing Conference, EDTM 2020 ; Conference Date: 6 April 2020 Through 21 April 2020; Conference Code:161190
Keywords:	Manufacture; Semiconductor junctions, Device architectures; Field effect transistor (FETs); High power electronic applications; Metal-semiconductor junctions; Printed electronics; Printing resolution; Solution-processed; Vertical transports, Power field effect transistors
Department/Centre:	Division of Mechanical Sciences > Materials Engineering (formerly Metallurgy)
Date Deposited:	10 Nov 2020 11:37
Last Modified:	10 Nov 2020 11:37
URI:	http://eprints.iisc.ac.in/id/eprint/67007

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