Threshold Voltage Shift in a-Si:H Thin film Transistors under ESD stress Conditions

Sinha, R and Bhattacharya, R and Sambandan, S and Shrivastava, M (2020) Threshold Voltage Shift in a-Si:H Thin film Transistors under ESD stress Conditions. In: 2020 IEEE International Reliability Physics Symposium, IRPS 2020, 28 April 2020 - 30 May 2020, Dallas, TX, USA.

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Abstract

We present physical insights into the instability behavior of hydrogenated amorphous TFTs under ESD stress using real-time current-voltage and capacitance-voltage characterization. A threshold voltage increase under moderate stress and a recovery under high stress is investigated. Impact of gate-bias and device dimension is explored. Physics of gate-bias annealing and an associated device recovery is explored. Finally, we investigate the instability behavior in a-Si:H gated diodes and explore the role of self-heating on their reliability. © 2020 IEEE.

Item Type:	Conference Paper
Publication:	IEEE International Reliability Physics Symposium Proceedings
Publisher:	Institute of Electrical and Electronics Engineers Inc.
Additional Information:	Conference of 2020 IEEE International Reliability Physics Symposium, IRPS 2020 ; Conference Date: 28 April 2020 Through 30 May 2020; Conference Code:161550
Keywords:	Bias voltage; Capacitance; Electrostatic devices; Reliability; Thin film circuits; Thin film transistors; Threshold voltage, A-Si:H thin film transistor; Capacitance voltage; Current voltage; ESD stress; Gated diodes; High stress; Self-heating; Threshold voltage shifts, Electrostatic discharge
Department/Centre:	Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology) Division of Physical & Mathematical Sciences > Instrumentation Appiled Physics
Date Deposited:	20 Dec 2024 10:07
Last Modified:	20 Dec 2024 10:07
URI:	http://eprints.iisc.ac.in/id/eprint/66175

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