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Micro-Architectural support for High Availability of NoC-based MP-SoC

Singh, R and Ranga, SV and Patil, S and Krishna, M and Mehta, M and Anoop, MN and Nandy, SK and Haldar, C and Narayan, R and Neumann, F and Baufreton, P (2019) Micro-Architectural support for High Availability of NoC-based MP-SoC. In: 2019 IEEE/AIAA 38th Digital Avionics Systems Conference (DASC), 8-12 Sept. 2019, San Diego, CA, USA, USA.

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Official URL: https://dx.doi.org/10.1109/DASC43569.2019.9081632


In this paper, we focus on increasing the availability of Multi-Processor System on Chip (MP-SoC) for executing user applications, even when some components of the system are faulty. A Network-on-Chip (NoC) provides high bandwidth communication substrate for the multitude of components/modules in such MP-SoCs. Health of such MP-SoC, and hence its availability, is largely dependent on the health of the NoC. We consider an NoC comprising a bidirectional toroidal mesh interconnection of routers. We use a distributed built-in-self-test to identify faulty communication links. We use information so obtained to determine healthy subsystems that can be made available for executing user applications. This feature is key for enhancing availability of MP-SoCs. We realize this feature as a micro-architectural enhancement in MP-SoC that incurs an insignificant hardware overhead of less than 2. Latency incurred for analyzing availability of MP-SoC is also insignificant. We functionally validate our proposal by emulating the system on a FPGA device and demonstrate increase in availability of the MP-SoC. © 2019 IEEE.

Item Type: Conference Paper
Publication: AIAA/IEEE Digital Avionics Systems Conference - Proceedings
Publisher: Institute of Electrical and Electronics Engineers Inc.
Additional Information: cited By 0; Conference of 38th IEEE/AIAA Digital Avionics Systems Conference, DASC 2019 ; Conference Date: 8 September 2019 Through 12 September 2019; Conference Code:159581
Keywords: Built-in self test; Digital avionics; Programmable logic controllers; Routers; Semiconductor device manufacture; Systems analysis, Architectural enhancement; Architectural support; FPGA devices; Hardware overheads; High availability; High bandwidth communication; Multi processor system on chips; Network-on-chip(NoC), Network-on-chip
Department/Centre: Division of Interdisciplinary Sciences > Computational and Data Sciences
Date Deposited: 27 Oct 2020 07:24
Last Modified: 27 Oct 2020 07:24
URI: http://eprints.iisc.ac.in/id/eprint/65663

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