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Bitwidth customization in image processing pipelines using interval analysis and SMT solvers

Purini, S and Benara, V and Choudhury, Z and Bondhugula, U (2020) Bitwidth customization in image processing pipelines using interval analysis and SMT solvers. In: 29th ACM SIGPLAN International Conference on Compiler Construction, 22 - 23 February 2020, San Diego; United States, pp. 167-178.

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Official URL: https://doi.org/10.1145/3377555.3377899


Unlike CPUs and GPUs, it is possible to use custom fixedpoint data types, specified as a tuple (α, β), on FPGAs. The parameters α and β denote the number of integral and fractional bitwidths respectively. The power and area savings while performing arithmetic operations on fixed-point data types are well known to be significant over using floatingpoint data types. In this paper, we propose a hybrid approach involving interval analysis and SMT solvers, for estimating integral bitwidths at different compute stages, in an image processing pipeline, specified using a domain-specific language (DSL) such as PolyMage. The DSL specification facilitates the compiler analysis to infer the underlying computational structure with ease. We also propose a simple and practical profile-driven greedy heuristic search technique for fractional bitwidth analysis. Using the Horn-Schunck Optical Flow benchmark program, we demonstrate where the conventional range analysis approaches fail, and how we overcome them using the hybrid technique proposed in this paper. The integral bitwidth estimates provided by the hybrid technique on the optical flow benchmark are up to 3x times better when compared with interval analysis. © 2020 Association for Computing Machinery.

Item Type: Conference Paper
Publication: CC 2020 - Proceedings of the 29th International Conference on Compiler Construction
Publisher: Association for Computing Machinery, Inc
Additional Information: Copyright of this article belongs to Association for Computing Machinery, Inc
Keywords: Digital subscriber lines; Field programmable gate arrays (FPGA); Fixed point arithmetic; Heuristic algorithms; Optical data processing; Optical flows; Pipelines; Problem oriented languages; Program compilers, Arithmetic operations; Bit-Width; Computational structure; Domain specific languages; Floating-point data; Image processing pipeline; Interval analysis; Smt solvers, Pipeline processing systems
Department/Centre: Division of Electrical Sciences > Computer Science & Automation
Date Deposited: 07 Apr 2021 09:38
Last Modified: 07 Apr 2021 09:38
URI: http://eprints.iisc.ac.in/id/eprint/65063

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