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Bias stress induced threshold voltage shift in buckled thin film transistors

Nair, A R and Anand, V and Sambandan, S (2019) Bias stress induced threshold voltage shift in buckled thin film transistors. In: 2019 IEEE Region 10 Conference: Technology, Knowledge, and Society, TENCON 2019, 17-20 October 2019, Hotel Grand Hyatt Kerala, pp. 78-81.

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Official URL: http://dx.doi.org/10.1109/TENCON.2019.8929275


Threshold voltage shift under bias stress is a significant instability mechanism in TFT based analog circuits. Here we study the impact of substrate curvature, due to buckling, on the threshold voltage shift in TFTs. The buckled structure is realized by texturing the gate metal layer in the form of periodic striations oriented along different directions. Preliminary studies under constant gate and drain bias indicate that the buckled TFTs suffer from a higher shift compared to planar devices. It is also observed that the angle of orientation of buckling influences the threshold voltage shift. It has been proposed that the observed trends in the experimental data are due to the vital role played by the contact resistance in buckled devices.

Item Type: Conference Paper
Publication: IEEE Region 10 Annual International Conference, Proceedings/TENCON
Publisher: Institute of Electrical and Electronics Engineers Inc.
Additional Information: Copyright of this article belongs to Institute of Electrical and Electronics Engineers Inc.
Keywords: Bias voltage; Buckling; Thin film circuits; Thin film transistors; Thin films, Bias stress; Drain bias; Gate metal layers; Instability mechanisms; Planar devices; Substrate curvature; Threshold voltage shifts, Threshold voltage
Department/Centre: Division of Physical & Mathematical Sciences > Instrumentation Appiled Physics
Date Deposited: 11 Feb 2020 11:46
Last Modified: 11 Feb 2020 11:46
URI: http://eprints.iisc.ac.in/id/eprint/64450

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